The invention relates to BIFET .RTM.integrated circuit (IC) devices. This class of IC employs conventional bipolar junction transistors (BJT's) in combination with junction field effect transistors (JFET) devices to produce high performance circuits. In an operational amplifier (op-amp) circuit the offset voltage (V.sub.OS) is defined as the differential input voltage required to produce a reference output voltage (usually ground potential in a dual voltage power supply). Typically, the IC device is trimmed to bring the V.sub.OS into specification. U.S. Pat. No. 4,618,833 discloses an offset trim, using zener zapping, that can be employed at either wafer probing, in the IC manufacturing process, or, following device assembly, to reduce V.sub.OS to a desired value without changing the V.sub.OS temperature drift.
The basic JFET structure employed in BIFET IC devices is disclosed in U.S. Pat. No. 4,496,963 and an improved version is disclosed in U.S. Pat. No. 4,176,368. The teachings in the above three patents are incorporated herein by reference.
In a patent application, Ser. No. 571,378, filed Aug. 21, 1990, and titled USER-PROOF POST-ASSEMBLY OFFSET VOLTAGE TRIM, means for providing a post assembly offset trim is disclosed. After trimming, the trim circuit can be deactivated so that no further offset change can be produced. This avoids inadvertent user access to the trim circuit and, thus, "user-proofs" the IC. The teaching in this patent application is also incorporated herein by reference.
The JFET devices employed in op-amp circuits are constructed in a process that also creates the well-known bipolar junction transistor (BJT) elements along with other IC component elements. The JFETs provide device parameters that are well-known. For example, the gate pinch-off voltage V.sub.P is defined as the gate to source voltage that will produce a specified drain cutoff current at a specified source to drain voltage. The saturation current (I.sub.DSS) is defined as the source to drain current that flows at a specified source to drain voltage and zero gate to source voltage. These parameters vary significantly in the manufacturing process and it is desirable to provide trimming to bring the op-amp characteristics into specification as part of the manufacturing process. Typically, the IC is energized and its performance measured. If the characteristics are within the specification, nothing is done. If the specifications are not met, trimming is performed to alter the characteristics so as to bring them within the specification. If the trim range is insufficient to provide the desired characteristics the IC is regarded as a reject.